CLK_ENA=Val_0x0, CLK_DIVISOR=Val_0x0, CLK_SEL=Val_0x0
CDC Pixel Clock Control Register
| CLK_ENA | Pixel clock enable 0 (Val_0x0): Clock disabled 1 (Val_0x1): Clock enabled |
| CLK_SEL | Pixel clock select 0 (Val_0x0): Select 400 MHz clock source (SYST_ACLK) 1 (Val_0x1): Select 480 MHz clock source (PLL_CLK3) |
| CLK_DIVISOR | Pixel clock divisor n: Clock divided by n 0 (Val_0x0): Illegal values 1 (Val_0x1): Illegal values 2 (Val_0x2): Clock divided by 2 3 (Val_0x3): Clock divided by 3 |